`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/06/18 17:32:47
// Design Name: 
// Module Name: DDS
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module DDS(
    input clk,
    input rst_n,
    input [31:0] Fword, //Ƶ�ʿ�����A
    input trigger,
    output data
    );
    //160M clk, output 10M clk, div=16
    (*mark_debug = "TRUE"*)(* KEEP = "TRUE" *) reg [43:0] r_Fword;

    reg [43:0] cnt;
 
    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
            r_Fword<=44'h10000000000;
         else if(trigger)
         //ֻ���ض�ʱ�̸���Ƶ��
            if(Fword[31]==1'b1)
                r_Fword<= 44'h10000000000 + {12'b1111_1111_1111, Fword}; //负数
            else
                r_Fword<= 44'h10000000000 + Fword; //正数
         else
            r_Fword<=r_Fword;
    end
 

    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
            cnt<=44'd0;
        else
            cnt<=cnt+r_Fword;
    end
    
    assign data = cnt[43];
    
endmodule
